Logic Synthesis for FSM-Based Control Units: 53 (Lecture Notes in Electrical Engineering)

Code of microinstruction is represented as a part of current state code and code of microinstruction inside of current subset. It leads to realization of FSM as s double-level structure. It leads to diminishing of number of variables required for encoding of microinstructions. Such approach permits to decrease the number of required outputs of combinational part of FSM.

Baranov, Logic Synthesis for Control Automat. Kluwer Academic Publishers, Lecture Notes in Electrical Engineering. Upper Saddle River, NJ: Barkalov, "Structural decomposition of finite state machines," Electronics and Telecommunications Quarterly , vol. Moore, "Gedanken-experiments on sequential machines," in Automata Studies , ser.

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Such an approach allows elimination of dependence among states and microoperations. As a result, both circuits for generation of input memory functions and microoperations are optimized. An example of the proposed method application is given.

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Abstract — The method is proposed for reduction of hardware amount in logic circuit of Moore finite state machine. The model of Moore finite state machine FSM [1] is often used during the digital control systems realization [2, 3]. The development of microelectronics has led to appearance of different programmable logic devices [4], used for implementing FSM circuits. In this case the circuit is implemented using customized matrices using the principle of distributed logic [7]. One of the ways to solve this problem is optimal coding of FSM [2].

However this approach does not allow optimization of the circuit generated output signals.

In this work some new optimization method is proposed. It is based on representation of the next state code as a concatenation of codes for class of pseudoequivalent states and vertex where this collection is generated.

Such an approach allows reducing of hardware amount in both parts. Manuscript received October 9, A control algorithm to be implemented is represented by the graph-scheme of algorithms [1]. This table is a basis to. The register RG keeps state codes.

The area of BIMF can be decreased using the approach of optimal state encoding [8]. It permits to decrease the number of terms in system 1 up to H0, where H0 is the number of transitions for equivalent Mealy FSM.

The area of BMO can be decreased due to refined state encoding [9]. It is possible some outcome of encoding, when the matrix M 4 is absent. But these methods cannot be used together. In this article the method is proposed permitting mutual area decrease for both blocks of FSM. One of Moore FSM features is existence of pseudoequivalent states [2], which are the states with the same transitions by the effect of the same inputs. Such states correspond to the control algorithm operator vertices [1], outputs of which are connected with an input of the same vertex.

Let us code set Yq with binary code K Yq having Ry bits, where. Let us use the following relation a on this set E1.

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Let us encode each vertex bq e Cj by the binary code K bq having. In this case, the code for state am e A can be represented as:.

Logic Synthesis For Fsm Based Control Units

Each function Bi e B is represented as the following. The matrix M6 implements the input memory functions. The matrix M8 implements functions yn e Y, depending on terms Aq e Yo. There are some positive features in the proposed method. Now codes of collections of microoperations do not depend on state codes.

Synthesis of FSMs Based on Architectural Decomposition with Joined Multiple Encoding

The number of rows. It allows such their encoding that diminishes the area occupied by BIMF. As it was mentioned, it is enough.